The present invention relates to a circuit for use in an LSI such as a microprocessor or digital signal processor (DSP) to correct errors that have been found in data stored on some storage medium like a masked ROM for the LSI.
Recently, the number of devices integrated together in a digital LSI, like a microprocessor or DSP, has been rising steeply and a memory circuit built in that LSI has its storage capacity increased year after year. Among other things, a masked ROM has a storage capacity much greater than that of a memory of any other type, and is mainly used as storage of a program to be executed by a processor.
As its name signifies, a masked ROM is an electrically non-alterable, read-only memory. So a program to be executed by its host processor or data required for that purpose is written on a ROM of this type while the LSI including the ROM is being fabricated. However, the greater the size of a program to be written, the more likely the program contains some errors. Accordingly, it has become more and more difficult to eliminate errors from a program of that huge size while an LSI is being fabricated. Thus, where errors have been found in a program or data that was stored on a masked ROM while an LSI was being fabricated, those errors should be corrected in some way or other when the LSI is operated.
FIG. 7 is a block diagram illustrating a known stored data modifier. A microprocessor 62 outputs an address signal SAD, specifying the address of data to be read out from a masked ROM 61, to the masked ROM 61 and an address comparator 65. In response to the address signal SAD, the masked ROM 61 outputs the data, which has been stored at the address specified by the address signal SAD, as a ROM data signal SROM to a selector 68. An address register 66 outputs a reference address signal to be compared to the address signal SAD. On receiving the address signal SAD and reference address signal, the address comparator 65 compares these signals to each other. And if the comparator 65 finds these signals matching, the comparator 65 outputs a correspondence signal SCI to the selector 68. If the selector 68 has received this correspondence signal SC1, the selector 68 selectively delivers the output of a data register 69 as a data signal SDT to the microprocessor 62. Otherwise, the selector 68 selectively outputs the ROM data signal SROM as another data signal SDT to the microprocessor 62.
When the data modifier shown in FIG. 7 finds an error in the program or data stored on the masked ROM 61, the modifier specifies the address associated with the error on the address register 66 and stores substitute correction data on the data register 69. In this case, where the microprocessor 62 has specified the address of error-free data, the address comparator 65 does not find the address signal SAD and the reference address signal matching. Accordingly, the ROM data signal SROM, output from the masked ROM 61, is delivered to the microprocessor 62. However, where the microprocessor 62 has specified the address of data containing an error, the address comparator 65 does find the address signal SAD and the reference address signal matching. As a result, the correction data, which has been pre-stored in the data register 69, is sent to the microprocessor 62. In this manner, the erroneous program or data stored on the masked ROM 61 can be modified.
In the known data modifier, if the microprocessor 62 has specified the address of data containing an error, then the erroneous data, read out from the masked ROM 61, is replaced at a time with the correction data that has been stored on the data register 69.
Suppose the masked ROM 61 of this data modifier outputs a data word with a multi-byte width, e.g., a 4-byte width. That is to say, let us suppose that the masked ROM 61 should read out 4-byte data at a time as a data word. In that case, if a 4-byte data word output contains errors, then the 4-byte data word, starting at an address represented by a multiple of four (which will be herein called a “4-byte-aligned address” or an “access boundary”), is replaced at a time. Then, the erroneous data word cannot be modified on an arbitrary unit. In other words, the data word to be replaced cannot start at an arbitrary address.
The microprocessor may issue a set of instructions of various lengths. That is to say, the number of bytes of one operation code for an instruction may be different from that of another. In that case, an operation code for an instruction included in the set may require reading data, starting at a non-4-byte-aligned address and covering two or more data words, from the masked ROM. Accordingly, if an instruction requires data covering a storage area, including, but not starting at, a 4-byte-aligned access boundary on the masked ROM, then it is difficult for the known data modifier to modify the data required even when the number of bytes of the instruction is four less.